1. Field
The present disclosure generally relates to integrated circuit design. More specifically, the present disclosure relates to reconfiguration of co-processor cores for general purpose processors.
2. Background
The popularity of computing systems continues to grow and the demand for improved processing architectures likewise continues to grow. The ever-increasing demand for improved computing performance/efficiency has led to various improved processor architectures. For example, multi-core processors are now more prevalent in the computing industry and used in various computing devices, such as servers, personal computers (PCs), laptop computers, personal digital assistants (PDAs), wireless telephones, and other like wireless mobile devices. As described herein, wireless mobile devices include, but are not limited to, mobile phones, hand-held personal communication systems (PCS) units, portable data units (e.g., personal data assistants), GPS enabled devices, navigation devices, music players, video players, entertainment units, or any other battery powered device that stores or retrieves data or computer instructions, or any combination thereof.
Balancing power and performance in wireless mobile devices, specifically, trading off power for performance by operating at a lower power and/or frequency is a challenge to the design of wireless mobile devices. Designers of wireless mobile devices are also constrained by the size and weight of batteries. The size and weight limitations are generally due to the increasing power consumption of the device hardware. Recent hardware architectural improvements may ease the balancing of power and performance when designing wireless mobile devices.
Previous CPUs (central processing units) featured a single execution unit to process instructions of a program. More recently, computer systems are being developed with multiple processors to improve the computing performance of the system. In some instances, multiple independent processors may be implemented in a system. In other instances, a multi-core architecture may be employed, in which multiple processor cores are amassed on a single integrated silicon die. Each of the multiple processors (e.g., processor cores) can simultaneously execute program instructions. This parallel operation of the multiple processors can improve the performance of a variety of applications.
A multi-core CPU combines two or more independent cores into a single package comprised of a single piece silicon integrated circuit (IC), referred to as a die. In some instances, a multi-core CPU may comprise two or more dies packaged together. A dual-core device contains two independent microprocessors and a quad-core device contains four microprocessors. Cores in a multi-core device may share a single coherent cache at the highest on-device cache level or may have separate caches. The processors also share the same interconnect to the rest of the system. Each “core” may independently implement optimizations such as superscalar execution, pipelining, and multithreading. A system with N cores is conventionally most effective when it is presented with N or more threads concurrently.
In some architectures, special-purpose processors that are often referred to as “accelerators” are implemented to perform certain types of operations. For example, a processor executing a program may offload certain types of operations to an accelerator that is configured to perform those types of operations efficiently. Such hardware acceleration employs hardware to perform some function faster than is possible in software running on a normal (general-purpose) CPU. Hardware accelerators may be designed for computationally intensive software code. Depending upon granularity, hardware acceleration can vary from small functional units to large functional blocks. Examples of such hardware acceleration include blitting acceleration functionality in graphics processing units (GPUs) and instructions for complex operations in CPUs.
Application-specific integrated circuits (ASICs) are conventionally implemented as custom designs. An ASIC is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, an ASIC may be implemented as a chip that is designed solely to run a wireless mobile device (e.g., a cellular telephone). Designers of digital ASICs may use a hardware description language (HDL) such as Verilog or VHDL, to describe the functionality of ASICs. Once a design is completed and a mask set produced for a. target chip, an ASIC is created. The configuration is created once. If a new configuration is specified, an entirely new design is specified. Thus, ASICs are not field-programmable.
Various devices are known that are reconfigurable. Examples of such reconfigurable devices include field-programmable gate arrays (FPGAs). A field-programmable gate array (FPGA) is a well-known type of semiconductor device containing programmable logic components called “logic blocks”, and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates, or more complex combinational functions such as decoders or simple mathematical functions. In some FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memories. A hierarchy of programmable interconnects allows logic blocks to be interconnected as desired by a system designer. Logic blocks and interconnects can be programmed by the customer/designer, after the FPGA is manufactured, to implement any logical function, hence the name “field-programmable.”